1. Field of the Invention
The present invention relates to a ramp wave generating circuit for vertical scanning in a television receiver and various kinds of monitoring instruments (referred to as television receiver and the like hereafter), particularly to a vertical ramp wave generating circuit improving interlace characteristics.
2. Description of the Related Art
A vertical ramp wave generating circuit according to the conventional example is shown in FIG. 5. A constant current source 1 supplies constant current I1 to a capacitor 3, and a constant current source 2 lets charge current I2 flow to a ground GND from the capacitor 3 when a switch SW1 closes. Fundamentally, by opening and closing the switch SW1, ramp wave voltage generates at a terminal 9 of the capacitor. Here, a circuit construction for opening and closing the switch SW1 is the followings.
Terminal voltage of the capacitor 3 is supplied to an inversion-input terminal (xe2x88x92) of a differential amplifier 4 for level-detecting, and to non-inversion input terminal (+) thereof, designated reference voltage Vref is supplied. Symbol 7 is a RS flip-flop supplying control signal for opening and closing the switch SW1. To a reset terminal R thereof, a designated reset pulse signal is supplied as a trigger signal, and on the other hand, to a set terminal S, level detecting output of the above-mentioned differential amplifier 4 is supplied.
Operation of the vertical ramp wave generating circuit having the above-mentioned construction will be described referring to FIG. 5 and operation timing chart shown in FIG. 6. When reset pulse signal (xe2x80x9cHxe2x80x9d level for example) generates, the pulse signal is held by the RS flip-flop 7 so that the switch SW1 closes responding on output Q (xe2x80x9cHxe2x80x9d level) of the RS flip-flop 7. Thus, discharge current I2 flows.
Then, output of the differential amplifier 4 is inverted when voltage of the terminal 9 decreases to reference voltage Vref. As the result, the RS flip-flop 7 is set, output Q of the RS flip-flop 7 is made xe2x80x9cLxe2x80x9d, and the switch SW1 opens and discharge current I2 is cut off responding on this. Thus, the capacitor 3 is charged by the constant current source 1. Because of that, voltage of the terminal 9 rises so that ramp wave starts to generate.
However, disturbance of horizontal frequency fh component generates in television receiver and the like. Here, one image picture consists of two fields, an even field and an odd field in the television receiver and the like interlacing. As the disturbance of fh component generates shifting xc2xd vertical period in theses fields, interlace characteristics happens to get worse when the disturbance of fh component including in any of fields occurs at starting timing of ramp wave generating.
That is, when disturbance of fh component shown in FIG. 7 generates, level of reference voltage Vref changes. Then, because the differential amplifier 4 carrying out level-detecting outputs invertedly at point A (point where reference voltage Vref ramp wave shifted by disturbance of fh component crosses, shifted voltage xcex94V generates. When the shifted voltage xcex94V exceeds allowance, interlace characteristics gets worse.
Then, an object of the invention is to provide a vertical ramp wave generating circuit improving interlace characteristics. Further another object is to provide a vertical ramp wave generating circuit suitable for IC.
The vertical ramp wave generating circuit for generating ramp wave for vertical deflection according to the invention is characterized in providing a capacitor for generating ramp wave, a constant current source for supplying constant current to said capacitor for generating ramp wave, voltage fixing means for discharging said capacitor for generating ramp wave and for fixing a terminal of the capacitor by force to the designated reference voltage, and a counting circuit enabling to output control signal having pulse width corresponding to desired waiting time, and by that terminal voltage of said capacitor for generating ramp wave is fixed to said reference voltage while waiting time set by said counting circuit, by operating said voltage fixing means corresponding to control signal output by said counting circuit.
According to the means, as the terminal voltage of the capacitor for generating ramp wave is fixed to reference voltage, even if disturbance of fh component generates at starting point of ramp, the terminal voltage of the capacitor for generating ramp wave is fixed again to reference voltage after the disturbance is distinguished while desired waiting time. As the above-described waiting time is set by the counting circuit, it is possible to determine accurately starting timing of ramp and to improve interlace characteristics surely.